The invention relates to memory cells, and more particularly, to memory cells with vertical transistor and capacitor and fabrication methods thereof.
Memory devices, such as dynamic random access memory (DRAM), for non-volatile storage of information, are currently in widespread use in a myriad of applications.
A conventional DRAM consists of a transistor and a capacitor, with electrical charges moving in or out of the capacitor during reading or writing. Typically a deep trench capacitor is used to reduce the size of a memory device. The capacitor is disposed in the deep trench bottom, the transistor is disposed at the deep trench top, and a thin dielectric layer, such as trench top oxide (TTO) layer, acting as an electrical insulating layer is disposed between the capacitor and the transistor.
FIGS. 1A-1F are cross sections of a conventional method for fabricating a memory cell with vertical transistor and capacitor. Referring to FIG. 1A, a semiconductor substrate 100 such as a single crystalline silicon wafer is provided with a pad silicon oxide 101 and a pad silicon nitride 102 thereon. A deep trench 110 is formed in the semiconductor substrate 100 employing the pad silicon oxide 101 and the silicon nitride 102 as mask. A storage capacitor 105 is formed at the bottom of the deep trench 110. A silicon oxide layer 104 is formed on the storage capacitor 105. A doped polysilicon layer 107 is formed on the silicon oxide layer 104 electrically coupling the storage capacitor 105. A trench top oxide (TTO) layer 108 is formed on the doped polysilicon layer 107 isolating the storage capacitor 105 and vertical transistor.
A diffusion region (not shown) is formed at sides of the TTO layer 108 in the semiconductor substrate 100. The diffusion region can serve as a drain of the vertical transistor. Next, a gate oxide layer 112 is conformably formed on the sidewalls of the deep trench 110.
Referring to FIG. 1B, a doped polysilicon layer 114 is formed in the deep trench 110 to serve as a gate of the vertical transistor. Next, the doped polysilicon layer 114 is planarized to expose the pad silicon nitride layer 102. The doped polysilicon layer 114 is formed by chemical vapor deposition (CVD). Since the doped polysilicon layer 114 is deposited from the sidewalls to a central region of the deep trench 110, the structure at the central region 115 of the deep trench 110 is less compact, thereby causing high resistance in the gate.
Referring to FIG. 1C, the doped polysilicon layer 114 and gate oxide layer 112 are etched back until lower the level of the semiconductor substrate 100 exposes a portion of the sidewalls of the trench and the pad silicon oxide 101 and the silicon nitride 102.
Referring to FIG. 1D, a silicon nitride layer 120 is conformably formed on the semiconductor substrate 100 covering the doped polysilicon layer 114, the gate oxide 112, the sidewall of the trench, the pad silicon oxide 101 and the silicon nitride 102. Next, the silicon nitride layer 120 is isotropically etched back to form a collar silicon nitride 120′ on the sidewalls of the trench. Silicon nitride residue 120″ accumulated at the central region of the trench is, however, quite difficult to remove, as shown in FIG. 1E.
Referring to FIG. 1F, a doped polysilicon layer 130 is formed in the trench, electrically coupling the gate 104 to serve as interconnect between the gate 104 and a word line (not shown). The neck R1 among the doped polysilicon layer 130, the gate 104, and the collar silicon nitride 120′ has high impedance causing greater power consumption and energy loss at high operating frequency. Conversely, an interface R2 between the residue silicon nitride 120″ and the gate 114 at center of the trench can cause open circuits in the memory cell.